A map of the Rigol DHO800/DHO900 hardware: what the parts are, how a signal travels through them, and how the logic analyser and the generator fit in.
The big picture
The scope is built around two chips. An FPGA handles everything that has to happen at sample speed: it takes the ADC data, watches for the trigger, fills the memory and runs the generator. An RK3399 processor, six cores and about 4 GB of memory, the same class of chip as in a tablet, runs Linux with the screen, the keys, the network and the mathematics.
The two meet over PCIe. The processor sets the FPGA up through registers, tells it to record, and later reads the finished record. It never sees samples as they arrive.
analog sampleslogic analyser linesgenerator signalsample clockcontrol eventsset-up buses
The whole scope. Signals run left to right; the generator runs right to left. The FPGA does everything that has to keep up with the sample clock. The processor only sets up, reads finished records and draws them.
One analog channel
The front end (one RT1642 per channel) makes any input fit the ADC: it selects the coupling and an input path, sets the gain for the V/div, adds the offset with its own DAC, and limits the bandwidth. It is set over a slow serial bus, so changing V/div takes real time.
The ADC turns the four front ends into 12-bit numbers and sends them to the FPGA on 28 serial lanes. The timing of each lane is measured at every start, because at these speeds every path differs a little.
One channel. The memory holds what the ADC delivered. The digital gain and offset correction comes only on the way out, when a record is read.
Why the sample rate depends on the channels
The ADC has eight cores. With one channel they all sample it in turn, which is what gives 1.25 GSa/s. More channels share the cores, so the rate and the memory per channel fall. Two channels take the even and the odd cores, whichever two they are. Three channels run as four, with one slot unused.
Acquisition: record, then play
The memory works like a tape loop. While armed, samples run in and the oldest fall out, so the part before the trigger is always there. When the trigger fires, the FPGA keeps recording for the post-trigger part and stops. Only then can the processor have the record played to it.
Recording and reading never happen at the same time. The memory cannot be played while it records, so each record costs a full stop and arm cycle. That cycle, not the ADC, limits the waveform rate: in one test with a 1 kHz signal about 30 records per second as single frames, about 800 in batches.
The read path sits between the memory and PCIe. For a live picture it thins out a long record by a factor or stretches a short one by interpolation, so that the transfer stays small. For a full record it is set to pass everything through unchanged. Its settings have to match the read exactly: the FPGA sends a fixed number of points per frame, and a frame that cannot fill it never ends.
In roll and scan mode this changes: at slow time bases the FPGA streams chunks continuously, and the processor builds the moving picture from them.
Trigger
The trigger unit decides when a record is complete. It is built from simple parts that combine into all the trigger types:
Part
What it does
Comparators
Two per analog channel, level A and level B, which is how window and slope triggers get two levels. LA lines use the pod comparators instead. The EXT input, where a model has one, has its own.
Events A and B
Each picks comparators, an edge and a pattern over all channels and LA lines (high, low, don't care, combined by AND, OR, NOR).
Time conditions
Greater than, less than, inside, outside, timeout. Time ticks are 1.6 ns and 6.4 ns.
Holdoff and auto
Holdoff blocks the next trigger for a time. Auto fires by itself when nothing else does, so the screen keeps moving.
Protocol triggers go a step further in software: the hardware fires on a line, and OOS looks for the wanted field in the decoded record.
Logic analyser
The optional PLA2216 probe adds 16 digital lines. A comparator turns each line into 0 or 1 against the threshold of its pod, and the FPGA packs them into one 16-bit word per sample.
The LA shares the memory with the analog channels, which is why switching it on costs depth. With a channel shown, the analog rate is halved as well.
The logic analyser. There is no per-line switch: with the LA on, all 16 lines are recorded and the choice of lines is only a display matter. Analog and LA words are never mixed: they arrive in separate reads, or in roll mode as separate chunks marked in their header.
Analog channels
Max. depth per channel, LA off
Max. depth per channel, LA on
1
125 M
31.25 M
2
62.5 M
12.5 M
3 or 4
31.25 M
10 M
Generator
The generator of the S models is a direct digital synthesiser in the FPGA. A phase counter steps through a table at a fixed clock; the size of the step sets the frequency. Software fills the table with the wanted shape, so the hardware does not know sine from square.
The generator. Every wave shape is only a different table in the same RAM; only noise uses a fixed phase step. Software picks the relay gear from amplitude and offset, and corrects levels with the factory calibration. There is no sweep, burst or sync output in hardware: the Bode plot sets one frequency after the other.
OOS limits the output to: sine, noise and DC up to 60 MHz, square 15 MHz, pulse 2 MHz, ramp 150 kHz, arbitrary 10 MHz. The output is switched on in a fixed order: relays safe, supply on, relay code, then the FPGA.
Clocks
One PLL chip, the TI LMX2582, makes the 1.25 GHz sample clock. Almost everything with a time in it follows from that number.
Clock
Value
Used by
ADC clock
1.25 GHz
ADC; the expected count of a self-check in the FPGA
ADC / 8
156.25 MHz, 6.4 ns
generator, roll stream, trigger time ticks
ADC / 2 assumed
625 MHz, 1.6 ns
fine trigger time ticks
ADC / 20 assumed
62.5 MHz
sample rate divider below 62.5 MSa/s
Start-up
The start, about 15 to 20 s by estimate. The FPGA needs its 10 s no matter what, so the rest of the system starts in parallel. Only after PCIe is up can the processor reach any FPGA register.
After a power cut the FPGA, the ADC and the front ends know nothing. OOS brings all of them up by itself; the stock system does not have to run first. Calibration values come from the factory files on the card, which OOS only reads, or from its own self-calibration.
All DHO800 and DHO900 models run the same software. They differ in what is fitted, and models.md has the full table.
DHO800
DHO900
S models (DHO914S, DHO924S)
Channels
2 or 4
4
4
Logic analyser port
no
yes
yes
Generator
no
no
yes
EXT trigger input
DHO802, DHO812
no
no
How sure is this
This page summarises the documents in docs/, which say for each statement how it is known. In short:
Part
State
Start-up, analog acquisition, trigger, roll and scan, generator sine
seen on a DHO924S
LA word format and rate
seen on a DHO924S under the stock system
LA under OOS, generator modulation and noise
tests on the host only
All other models
never run
All of this is known from the software side: the device tree, the registers and how the hardware answers. The part numbers of the ADC and the front ends come from there too and have not yet been read off the chips. The inside of the front ends and of the generator output stage is drawn only as far as the software can see it.